At the 2026 MiNaPAD Forum (June 3–4, Minatec Grenoble, France), CEA-Leti will occupy booth 1 to showcase its latest advances in next-generation chip integration and advanced packaging. Experts will be on hand to discuss six papers and posters covering eco-innovation, microbumps, fan‑out wafer‑level packaging (FO‑WLP), hybrid bonding, and related topics. Key on‑site demonstrations include STARAC, hybrid bonding, Chip‑in‑Flex, and FO‑WLP, targeting heterogeneous system‑in‑package architectures, multi‑chip quantum processor assemblies, chiplet‑based optical networks‑on‑chip, and other enabling integration technologies.

The detailed technical program features six CEA-Leti contributions. On June 3, a morning session in room D‑Chrome will examine pressure‑less silver sintering for power applications, specifically the influence of silver, gold, or copper surface finishes on microstructure and mechanical performance. Simultaneously, an extra‑auditorium session will present an overview of the French PEPR Packaging (INPACK) and ReNaPack projects. At noon in the main auditorium, a session will assess the environmental impact of 3D integration, reflecting the institute’s focus on sustainable electronics. The following day opens with new dielectric materials designed for low‑temperature hybrid bonding (9:45 a.m., K‑Chrome), followed by an investigation into wafer‑level downscaling of electroplated lead‑free microbumps for ultra‑fine‑pitch interconnects (11:45 a.m., M‑Chrome). The last paper, at 1:45 p.m. in the auditorium, describes a radar with integrated antennas built using a redistribution‑layer‑first FO‑WLP approach.

MiNaPAD is described as the premier international forum for micro/nano‑electronics packaging, assembly, design, and manufacturing, fostering cooperation and technical exchange. Questions can be directed to Jean‑Charles Souriau, CEA project manager for micro‑interconnections and packaging.

Beyond MiNaPAD, the article flags several other upcoming CEA‑Leti engagements. In Grenoble, a workshop on organoids and organoids‑on‑chip will be held September 29, and the LID World Summit will take place June 23–25. At PCIM, live demonstrations will highlight ultra‑thin power converters based on piezoelectric storage, a smart multilevel flying‑capacitor converter, a high‑power multilevel GaN DC‑DC converter for fuel‑cell‑to‑battery adaptation, and predictive maintenance using non‑invasive sensors, all set against CEA’s wide‑bandgap roadmap for applications from data centers to drones, automotive, aeronautics, space, and medical. A dry‑etching workshop will also take place in Grenoble. Finally, in San Jose, California, CEA‑Leti will present 11 papers, cementing its role as an indispensable research center in ultimate silicon integration.

From 6/3/2026 to 6/4/2026Minatec Grenoble, France

CEA-Leti experts will be onsite at booth 1 and available to discuss the findings of Six Papers and Posters Includes eco-innovation, microbumps, FO-WLP, packaging and hybrid bonding.​

COME AND MEET CEA-LETI'S EXPERTS​

This year, CEA-Leti’s booth will exhibit STARAC, Hybrid bonding, Chip-in-Flex, FOWLP. Come and discuss lastest achievements in terms of Next-Generation Chip Integration at MiNaPAD

Advanced packaging technology for heterogeneous System-in-Package (SiP)

A multi-chip assembly with quantum processor and control chips​​

Chiplet-based Optical Network on Chip (ONoC)​​​

An enabling technology for new architectures​​

DISCOVER CEA-LETI’S MAJOR SCIENTIFIC RESULTS

June 3, 2026 - 11:30 amSession D-Chrome

Pressure-less silver sintering for power application: impact of silver, gold or copper surface finishes on microstructure and mechanical performances

June 3, 2026 - 11:30 amSession Extra-Auditorium

PEPR Packaging (INPACK) and ReNaPack - Projects overview

June 3, 2026 - 12:00 pmSession C - ​Auditorium​​

Learn about 3D integration through its environmental impact​

June 4, 2026 - 9:45 amSession K-Chrome

New dielectric materials for low temperature hybrid bonding​

June 4, 2026 - 11:45 amSession M -Chrome

Investigation of wafer level downscaling challenges in electroplated lead-free microbumps for ultra-fine pitch interconnects

June 4, 2026 - 1:45 pmSession N-Auditorium

Radar with Integrated Antennas based on Fan-Out Wafer-Level Packaging RDL-First Integration

The Micro/Nano-Electronics Packaging and Assembly, Design and Manufacturing Forum  (MiNaPAD) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange.

More information on ​​MiNaPAD’s website

From 6/3/2026to6/4/2026​ |​Minatec Grenoble, France​

ContactJean-Char​les SOURIAU​:with any questions.​​

CEA Project Manager in the field of micro-interconnections and packaging

Event | Agenda|Y-Spot Partners, Grenoble, France

We are delighted to announce that CEA is hosting the "Organoids & Organoids-on-Chip" workshop at its Grenoble site on September 29, 2026.

Event|Maison Minatec, Grenoble, France

LID World Summit from 23 to 25 June offer you a front-row seat to our most recent advances. Join more than 1,250 semiconductor industry professionals at this three-day global event and come away equipped and inspired to innovate!​

We’re excited to welcome you back to PCIM!

Join us to discover our latest innovations through live demonstrations, including:- Ultra thin power converter based on piezoelectric storage,- Smart multilevel converter utilizing flying capacitor topology- High Power multilevel GaN DCDC converter for fuel cell to battery voltages adaptation- Predictive maintenance on power electronic based on non invasive sensors.Focus will be put on CEA Wide Band Gap roadmap and technologies to address high demand and challenges on power supplies. It addresses different applications from data center to drones going through automotive, aeronautic, spatial, medical.

Event|Minatec, Grenoble, France

The workshop gathers scientists, engineers and industry partners to discuss advances and challenges in dry etching, plasma processing and related technologies for semiconductor, MEMS and emerging applications.

Event | Agenda|San Jose, California, US

Avec 11 papiers, le Leti se positionne comme un centre de recherche incontournable dans le domaine de l'intégration ultime sur silicium.