CEA-Leti will bring a broad portfolio of advanced semiconductor research and hardware security demonstrations to multiple international events in 2026, with ESSERC in Palma de Mallorca (September 7–10) serving as the anchor conference. The institute, together with CEA-List, will showcase two hardware security tools: VASCO2, demonstrating silicon-embedded security innovations, and the SCIBE tool for security assessment of embedded systems’ interfaces.

At ESSERC’s technical sessions, CEA-Leti scientists will present five papers spanning next-generation device architectures and circuits. Highlights include a novel hybrid-channel CFET (complementary FET) stack fabricated via innovative wafer-to-wafer bonding and nanosheet patterning; a 3D sequentially integrated back-side illuminated CMOS image sensor with a source-follower pixel that mitigates floating-body effects and models pixel-level noise; BumbleBee, a 3 mW fused-kernel flash attention AI co-processor implemented in 18 nm FD-SOI CMOS; a statistical study of hafnium-zirconium-oxide-based ferroelectric capacitive memories integrated into the BEOL of a 22 nm FDSOI process; and an on-chip switched-capacitor converter topology that reduces power by 50% while expanding attack traces by 114× for security applications.

A dedicated half-day workshop on September 7, co-organized by the FAMES pilot line and the SiNANO Institute, will provide the first in-depth technical results from the development of 10 nm and 7 nm FD-SOI technologies under the “FDSOI Pilot Line Insights and Perspective” banner.

Beyond ESSERC, CEA-Leti will discuss sustainable integrated hardware and software at the END* symposium, highlight AI semiconductor scaling at Leti Innovation Days Tokyo under the theme “The AI-Chip Revolution,” and present three papers on heterogeneous integration at SEMICON Taiwan 2026 as part of the Choose France Pavilion. The institute also hosts the LID World Summit in Grenoble (June 23–25), bringing over 1,250 industry professionals together around the latest semiconductor advances. For ESSERC inquiries, contact François Andrieu.

From 9/7/2026 to 9/10/2026Palma de Mallorca, Spain

CEA-Leti in association with CEA-List, will showcase its hardware security innovations for silicon-embedded hardware, through the VASCO2 demonstrator, as well a​s its expertise in security assessment of embedded systems’ interfaces, through the SCIBE tool demonstrator.​​

DISCOVER CEA-LETI’S MAJOR SCIENTIFIC RESULTS AT ESSERC

Tuesday September 08, 202611:00 am - 1:00​ pmSala MAGNA​​

Fabien RozeSylvain BarraudJean-Michel PediniVincent LarreyFrank FournelJean-Michel Hartmann​Karine Abadie​

Fabrication of Hybrid Channel CFET Stack by Innovative Wafer-to-Wafer Bonding and Nanosheet Patterning​​​

Tuesday September 08, 2026​11:00 am - 1:00​ pmSala GRANADOS I​

Ahmed MachmachChristoforos TheodorouSébastien PlaceThomas NassietFrederic LalanneChristian Gardin​​

Nmos SOI Source Follower Floating Body Effects Mitigation and Pixel Level Induced Noise Modeling in 3D Sequentially Integrated BSI CIS ​​​​​

Thursday September 10, 2026 10:40 am - 1:00 pmSala TURINA​

Joaquin A. CornejoFilipe PougetAmelie PoullotRaphael GrasDominique BousquetNicolas Lebouleux​Tarun Chawla​

BumbleBee: A 3 mW Fused-Kernel Flash Attention Edge AI Co-Processor in 18 nm FD-SOI CMOS​

Thursday September 10, 2026 10:40 am - 1:00 pmSala MAGNA​

Yann BeilliardLanig Le MeurSimone D’AgostinoLiam HosierSimon MartinCarine JahanFrançois AndrieuElisa Vianello ​

Statistical Study of HZO-Based Ferroelectric Capacitive Memories Integrated in 22 nm FDSOI BEOL​

Thursday September 10, 2026 10:40 am - 1:00 pmSala ALBENIZ

​Justin PabotYasser MoursyMaxime LecomteRomain Wacquez​Gaël Pillonnet​

On-Chip SCC Topologies for Security Enabling 50% Power Reduction and 114× Attack Traces​​

Meet FAMES at ESSERC 2026 in Mallorca​

On 7 September 2026, FAMES and the SiNANO Institute will host a dedicated half-day workshop entitled: “FDSOI Pilot Line Insights and Perspective” This session will be the first opportunity to present in-depth technical results from the FAMES Pilot Line on the development of 10 nm and 7 nm FD-SOI technologies. ​​

A dedicated workshop by FAMES & SiNANO Institute​

More information on ​​ESSERC’s website

From 09/07/2026 to 09/10/2026  |​Palma de Mallorca, Spain

Contact:François Andrieu​with any questions.​​

Event|Grenoble Scientific Polygon, France

Europe has the expertise and skills to promote a more responsible digital sector (frugality, regulation, ethics) that creates high-quality jobs. However, mastery of data is just as crucial as mastery of materials and energy when it comes to the operability and sustainability of disruptive digital components and integrated circuits. More sustainable integrated hardware and software solutions will be discussed at the END* symposium in the field of Information & Communication Technologies (ICT)

CEA-Leti has invested in multidisciplinary platforms with unique equipment and expertise. By leveraging advances in heterogeneous integration, new materials and photonics, we are driving semiconductor innovation and tackling the new challenges of disruptive AI markets and technologies.

During this 19th edition of Leti Innovation Days Tokyo, CEA-Leti’s CEO will celebrate R&D partnerships with its partners in Japan and explore new possibilities to support the Japanese semiconductor industry. This year’s theme is “The AI-Chip Revolution: Scaling Innovation in Semiconductors”.

High-level speakers and technical experts will present the latest advances through keynote speeches, seminars and live demos. Join us to enjoy lively networking and exchanges in a unique setting at the Residence of France in Japan.

CEA-Leti experts will be onsite at CEA-Leti's booth and available to discuss the findings of three papers on heterogeneous integration

Event|TaiNEX 1 & 2 – Taipei Nangang Exhibition Center, Taipei, Taiwan

CEA-Leti is participating in SEMICON Taiwan 2026, highlighting its latest advances in semiconductor technologies and reinforcing its long-standing commitment to scientific and industrial cooperation with Taiwan and the global semiconductor ecosystem. As part of the Choose France Pavilion, CEA-Leti contributes to promoting French excellence in technology research, innovation and technology transfer.

Event|Maison Minatec, Grenoble, France

LID World Summit from 23 to 25 June offer you a front-row seat to our most recent advances. Join more than 1,250 semiconductor industry professionals at this three-day global event and come away equipped and inspired to innovate!​